EPMC1: How to Design FPGA and ASIC Devices to Meeting System Performance

Dr. Hong Shi

Abstract

With increasing clock rate and bandwidth required to support memory interface such as DDR as well as mutli-gigahertz serial link such CEI and 10Gb PCIE, packaging as silicon interconnect faces daunting design challenges in meeting system performance spec while stays on cost effective target from manufacturing perspective. In this seminar we will start from top level system requirement to FPGA devices, and depict methodology in linking physical design rules to basic electrical parameters such as PDN impedance, mutual inductance, s-parameter, and eventually to end-user specs in language of timing closure, noise margin, and jitter. The emphasis will be given to analysis of different package structures and associated performance assessment. We will use examples of design and characterization to validate package designs to meet both performance and cost target.

Biography

Dr. Hong Shi is technical lead for the Packaging Technology Department at Altera Corporation. As manager of the Packaging group's electrical design team, Dr. Shi's responsibilities include developing the strategy for high-density and high-performance FPGA packaging, simulating system level electrical performance and establishing chip-package-board interconnect co-design capability. Before joining Altera, Dr. Shi worked at HP and Agilent Technologies where he was project leader for Agilent's first 40-Gbps digital communications analyzer module. He has published over 30 technical papers in areas of optoelectronics, microwave circuits and digital circuit packages. Dr. Shi obtained his BSEE from Xi'an Jiaotong University, MS Physics from DePaul University, and PhD in electrical engineering from CREOL College of Optics at University of Central Florida.